Sutherland, Ivan

Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)

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Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)
Fantastic Text
Blown away
Great Product
A very good book for designers or advanced students

Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)
Ivan Sutherland , Robert F. Sproull , and David Harris
Manufacturer: Morgan Kaufmann
ProductGroup: Book
Binding: Paperback

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ASIN: 1558605576

Book Description

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.

* Explains the method and how to apply it in two practically focused chapters.
* Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
* Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
* Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
* Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
* Presents a complete derivation of the method-so you see how and why it works.

Customer Reviews:

Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design) .......2006-11-05

This book was really easy to read and explained the concepts well in some areas. Part of this is perhaps my professor followed this book rather closely and synced it with his lectures. There were some areas that were very difficult to fully grasp without his lectures. One thing the book failed to do was fully describe assymetric sizing. They only described two input gates but never went into three input gates which is a little more tricker. There other areas where this occur-a concept would be described for only a simple case but it wouldn't go much deeper than that.

Fantastic Text.......2004-05-20

One of the best texts out there concerning a good way to judge a design in terms of its delay. Previous texts in VLSI have failed to really adequately describe how to address a design for optimum delay. This book makes up for this lack of content. A must read for anyone concerned with VLSI circuit design! Plus, its lots of fun to play with.

Blown away.......2000-12-26

This is without a doubt a must-have for CMOS logic and circuit designers. No doubt this will be on my desk for the forseeable future. The first two chapters present a basic introduction to the approach that is sufficient to gain a working knowledge. The remaining chapters delve into details such as applying the method to domino circuits, passgate logic, cells with unequal rise/fall times, and a complete derivation of the method. The authors are well known experts in the field of high speed circuit design, and David Harris' presentation of the material is far from bland and boring. This is one of the few technical books I had a hard time putting down. Highly recommended!

Great Product.......2000-11-19

A welcome addition to the field of VLSI with pratical and not ridiculous constraints to establish fast and efficient logic designs. The book could use some introduction topics in VLSI to make the book more broad and probably more appealing as a textbook.

A very good book for designers or advanced students.......1999-09-26

This book is a long overdue explanation of the "Logical Effort" approach to MOS circuit design invented by two of the authors, Sutherland and Sproull, in the late 80's. The technique presented is complete and powerful, and this book should be required reading for all persons involved in high-performance or low-power MOS digital design. Nevertheless, I would not recommend it for beginners without some of what the authors call "instruction from veteran designers." The main shortcoming of the book is a lack of organization---important points are sometimes made in seemingly unrelated sections, and the sections themselves do not always appear to follow the most logical arrangement---and it could stand a more thorough editing job to clean up some of the presentation. Sometimes, I felt that information that was presented in charts would have been much more powerful in graph form. A few of the graphs in the book are misleading (arbitrary scales and unmarked breaks in scales), and some of the mathematical terminology is imprecise. The fact that the authors picked, somewhat arbitrarily, a new definition of the technology delay parameter tau (instead of sticking to the definition established by Mead & Conway in their 1980 book) is annoying. Aspiring asynchronous designers should be cautioned that the two designs for an n-input Muller C-element contrasted in Section 11.2 are logically different. A section contrasting the uses of the logical effort method in synchronous and asynchronous designs would also be welcome. All in all, however, the book is very readable, and it is easy to follow. It would be effective as a textbook, and it is a most welcome addition to my library because it treats a difficult and important topic better and in more detail than any other published work.

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